1. Field of the Invention
This invention relates to an information processing apparatus, and more particularly to an information processing apparatus which operates with clock pulses from a clock oscillator.
2. Description of the Related Art
Where a conventional information processing apparatus which operates with clock pulses from a clock oscillator has a construction wherein a single clock oscillator is included, a failure of the clock oscillator disables the entire information processing apparatus. Therefore, another construction wherein redundant clock oscillators are provided so that the entire information processing apparatus is prevented from being disabled by a failure of one clock oscillator is conventionally proposed. For example, Japanese Patent Laid-Open No. 112322/1984 discloses an apparatus wherein a plurality of oscillators are provided and an output of a single normal one of the plurality of oscillators is selectively outputted by a supervising circuit which supervises clock pulses of the oscillators to detect a failure of any one of the oscillators.
FIG. 1 is a block diagram showing a circuit construction of the apparatus proposed in the document mentioned above. Referring to FIG. 1, reference numerals 511, 512 denote each an oscillator, 513, 515, 518, 520 denote each a stretcher whose output varies from "0" to "1" simultaneously when the input thereto varies from "0" to "1", but varies, when the input thereto varies from "1" to "0", from "1" to "0" after predetermined stretching time t.sub.x, 514, 519, 524 denote each a NOT (inverter) circuit, 516, 517, 521, 522, 523, 525 denote each a logical AND circuit, and 526 denotes a logical OR circuit.
Operation of the circuit shown in FIG. 1 is described below. FIGS. 2(a) and 2(b) illustrate output signals of oscillator 511, stretchers 513, 515, NOT circuit 514 and logical AND circuit 516 which are part of the circuit shown in FIG. 1.
Referring to FIGS. 2(a) and 2(b), (i), (n) illustrate the outputs of oscillator 511, (j), (o) illustrate the output of NOT circuit 514, (k), (p) illustrate the output of stretcher 513, (l), (q) illustrate the output of stretcher 515, and (m) (r) illustrate the output of logical AND circuit 516.
FIG. 2(a) shows timing waveforms when oscillator 511 stops its oscillation at time T.sub.A and thereafter the output thereof continuously exhibits "0". The period of the output signal of oscillator 511 is represented by t, and the stretching time of stretchers 513, 515 is represented by t.sub.x. Further, it is assumed that t/2&lt;t.sub.x.
Referring to FIG. 2 (a), the output of oscillator 511 is normal till time T.sub.A as seen from (i) and continuously exhibits 0 after time T.sub.A. The output of NOT circuit 514 is inverted from "1", "0" of the output of oscillator 511 and has such a waveform as seen from (j). When oscillator 511 is normal, "0", "1" are repetitively inputted to stretcher 513. However, as described above, the output of stretcher 513 varies instantaneously from "0" to "1" when the input to stretcher 513 varies from "0" to "1", but when the input varies from "1" to "0", the output varies from "1" to "0" after stretching time t.sub.x. Accordingly, where the input period is t, the time after the output varies from "1" to "0" until it varies from "0" to "1" is t/2 and is shorter than time t.sub.x. Consequently, the output of stretcher 513 continues to be "1". However, if the oscillation of oscillator 511 stops at time T.sub.A and the output of it varies to "0", then the output of stretcher circuit 513 varies from "1" to "0" after time t.sub.x after time T.sub.A as seen from (k) of FIG. 2(a). Meanwhile, to stretcher 515, a signal inverted from "1", "0" of the output of oscillator 511 by NOT circuit 514 is inputted. Accordingly, the input to stretcher 515 has a waveform which varies from "0" to "1" at time T.sub.A and thereafter keeps "1". In the case of this input, the output of stretcher 515 keeps "1" as seen from (l) which is different from the output of stretcher 513. Accordingly, the output of logical AND circuit 516 which is a result of logical ANDing of the outputs of stretchers 513, 515 is such as seen from (m).
Referring to FIG. 2(b), (n) illustrates the output of oscillator 511 when it stops its oscillation at time T.sub.B and the output thereafter exhibits continuous "1". The output of NOT circuit 514 is a signal inverted from input (n) thereto and is such as seen from (o). Accordingly, it is considered that (j), (i) in FIG. 2(a) are inputted to stretchers 513, 515, respectively, and from the reason described above, the outputs of stretchers 513, 515 are such as seen from (p), (q) respectively. As a result, the output of logical AND circuit 316 is such as seen from (r).
As described above, functional block A surrounded by broken lines in FIG. 1 which is composed of stretchers 513, 515, NOT circuit 514 and logical AND circuit 516 supervises the output of oscillator 511 and outputs "1" if the output of oscillator 511 is normal, but outputs "0" if the output of oscillator 511 is abnormal.
Also functional block B shown in FIG. 1 which is composed of stretchers 518, 520, NOT circuit 519 and logical AND circuit 521 has a same construction as that of functional block A, and supervises the output of oscillator 512 similarly and outputs "1" if the output of oscillator 512 is normal, but outputs "0" if the output of oscillator 512 is abnormal.
In the following description, functional blocks A, B are referred to as supervising circuits A, B, respectively. FIG. 3 illustrates output waveforms of different elements of the circuit shown in FIG. 1. FIG. 3 shows output waveforms of the different elements when such an abnormal condition as illustrated in FIG. 2(a) occurs with oscillator 511 while oscillator 512 is normal. (a) illustrates the output of oscillator 511, (b) the output of supervising circuit A, (c) the output of logical AND circuit 517, (d) the output of oscillator 512, (e) the output of supervising circuit B, (f) the output of NOT circuit 524, (g), (h) illustrate the outputs of logical AND circuits 523, 525, respectively, and (i) illustrates the output of logical OR circuit 526.
If oscillator 511 enters, at time T.sub.A, an oscillation stopping condition wherein the output thereof exhibits continuous "0" as seen in FIG. 3, then the output of supervising circuit A varies from "1" to "0" after time t.sub.x after time T.sub.A and has such a waveform as seen from (b). The output of logical AND circuit 517 is a result of logical ANDing between output (a) of oscillator 511 and output (b) of supervising circuit A and has such a waveform as seen from (c). In this instance, the output of supervising circuit A is used so as to pass the output of oscillator 511 if it is normal, but intercept it if it is abnormal.
Meanwhile, since the output of supervising circuit B of oscillator 512 exhibits "1" as seen from (e) because the output of oscillator 512 is normal. The output of NOT circuit 524 is an inverted signal from a result of logical ANDing of the outputs of supervising circuits A, B and has such a waveform as seen from (f). Also logical AND circuit 523 plays a same role as that of logical AND circuit 517 described above, and the output waveform thereof is such as seen from (g). Logical AND circuit 525 plays the following role based on the output of NOT circuit 524. In particular, if both oscillators are normal, then the outputs of supervising circuits A, B are "1", and the output of NOT CIRCUIT 524 is "0". Also the output of logical AND circuit 525 is "0", and the output of oscillator 511 is outputted from logical OR circuit 526. On the other hand, when the output of oscillator 511 is abnormal, the output of NOT circuit 524 is "1", and the output of oscillator 512 is made use of for the first time. Accordingly, the output of logical OR circuit 526 has such a waveform as seen from (h).
As seen from FIG. 2(b), this similarly applies also when the oscillator oscillates in a continuous "1" condition, and the output of a normal oscillator is selectively outputted.
Further, though not shown, by using the outputs of supervising circuits A, B, it is possible to report an abnormal condition of an oscillator to the outside of the apparatus. Consequently, a countermeasure can be taken against the abnormal condition of the oscillator before it gives rise to a malfunction of the apparatus, and constantly stable operation of the apparatus can be anticipated.
FIG. 4 is a block diagram showing another circuit construction of the apparatus proposed in the document mentioned hereinabove. In FIG. 4, like elements to those shown in FIG. 1 are denoted by like reference numerals. Referring to FIG. 4, reference numerals 831, 833 denote each a frequency-voltage converter, which outputs a voltage corresponding to a frequency of a waveform inputted thereto. Reference numerals 832, 824 denote each a level detector which discriminates whether or not there is an input voltage which remains within a set voltage which has a certain width and outputs, if there is an input voltage, "1", but outputs "0" if there is no input voltage.
Referring to FIG. 4, the outputs of oscillators 511, 512 are supervised by frequency-voltage converters 831, 833 and level detectors 832, 834, respectively. In particular, if the output frequency of oscillator 511 is normal, then the output voltage of frequency-voltage converter 831 is within the set voltage of level detector 832 which has the certain width, and level detector 832 outputs "1". Then, if the frequency of the oscillator drops, then also the output voltage of frequency-voltage detector 831 drops and this voltage becomes lower than the set value of level detector 832. Consequently, level detector 832 outputs "0". Accordingly, if frequency-voltage converter 831 and level detector 832 are used for the supervising circuits described in connection with the conventional apparatus described above, then not only stopping of the output of an oscillator, but also a drop or a rise of the output frequency can be detected. Accordingly, a higher effect can be anticipated.
However, the prior art described above has the following problems .
The first problem is that, when supervision of the oscillators is performed, an increase of the oscillation frequency of an oscillator cannot be supervised, or even if such supervision is possible, this is unreliable analog supervision and a fine displacement of the oscillation frequency cannot be supervised. This also applies to a drop of the oscillation frequency, and either supervision is possible only where the oscillation frequency drops lower than 1/2 or only unreliable analog supervision can be performed.
Further, also with regard to reporting of an error of an oscillator, it is only possible to report within the range of the supervision level mentioned above, and it is impossible also to set what degree of increase or drop of the oscillation frequency should be regarded as an error.
Therefore, if the oscillation frequency of an oscillator is displaced delicately, there is the possibility that this may give rise to various problems.
For example, if the oscillator frequency increases, then a clock frequency becomes higher, and this gives rise to a problem of a delay. Consequently, although the hardware is not in failure, an error is detected and operation is stopped, or illegal data are produced.
On the contrary, also when the oscillation frequency drops, this gives rise to various problems similarly. For example, as the performance of the system is dropped, the system is put into an overload condition and hence into a halted condition, or a calendar clock which is referred to during operation of the system is delayed from the actual time, and this may give rise to a malfunction particularly on an application which utilizes a network.